A Logic OR Gate or Inclusive-OR gate is a type of digital logic gate that has an output which is normally at logic level "0" and only goes "HIGH" to a logic level "1" when ANY of its inputs are at logic level "1". The output of a Logic OR Gate only returns "LOW" again when ALL of its inputs are at a logic level "0". The logic or Boolean expression given for a logic OR gate is that for Logical Addition which is denoted by a plus sign, (+) giving us the Boolean expression of: A+B = Q.
"If any one of Inputs is true the Output will be true"
3 Input OR gate Truth table :
TTL OR gate :
The TTL Logic gates are constructed by Transistor-Transistor Logic. Fig-2 shows a RTL- Resistor Transistor Logic for OR gate. Two Transistors and three Resistors can develop an OR gate logic. The Bases of the two transistors are used as the inputs after the resistors and the both emitters jointly gives the OR logic output.The TTL based OR gate IC is shown below :
- 74LS32 Quad 2-input
CMOS OR gate :
Three(3) p-type and three(3) n-type MOSFETs constructs a 2 input OR gate logic. The first 2 p-type and 2 n-type MOSFETs construct an NOR gate logic and the rest two p-type and n-type construct an Inverter logic. So the first portion gives NOR output and the second part getting that output gives OR output doing the NOT logic operation (inverting) see the Fig-3. The CMOS type OR gates are shown below :
- CD4071 Quad 2-input
- CD4075 Triple 3-input
- CD4072 Dual 4-input
OR gate analogy :
Fig-4 shows an analogy of OR logic gate. Which constructed by a battery, 2-switches(SPST) connected parallely and a electric bulb; where 2 switches are indicates OR inputs and the electric bulb as the OR output. If the switch A is closed and B is open the bulb will be bright. If again switch A is opened and B is closed the output will also be the same as previous, the bulb will be bright. When both switches(A and B)are closed the output will be bright. But if the both switches ( A and B) are opened the bulb will not be bright. That means this circuit follows the Truth table of an OR logic gate.