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| Written by : Ram Krishna Paul, B.Sc. in EEE, 25th | B | Day, SUB |
Experiment # 01NAME OF THE EXPERIMENT:Layout design of a CMOS Inverter. OBJECTIVES:1. To design the mask layout of CMOS inverter with equal rise time and fall time THEORY:CMOS Inverter: The CMOS inverter consists of an n-channel transistor and a p-channel transistor by interconnecting the gates. Where the width of nMOS is 2 times of pMOS. EXPERIMENTALLY OBTAINED:1. Mask layout of CMOS inverter with equal rise time and fall time: > Input-Output wave shape:
2. Parametric analysis:
> Fall delay from clock input to output:
> Frequency of node output:
3. Spice net list: CIRCUIT H:\RAM\installed softwares\microwind\2New Folder-2\mw03\Export Microwind\ram\ram-INV-3.MSK * * IC Technology: CMOS 0.35µm - 5 Metal * VDD 1 0 DC 3.50 Vclock input 6 0 PULSE(0.00 3.50 1.97N 0.03N 0.03N 1.97N 4.00N) * * List of nodes * "Output" corresponds to n°4 * "clock input" corresponds to n°6 * * MOS devices MN1 0 6 4 0 N1 W= 6.40U L= 1.00U MP1 4 6 1 1 P1 W= 6.00U L= 0.40U * C2 1 0 71.040fF C3 1 0 6.000fF C4 4 0 17.643fF C6 6 0 2.739fF * * n-MOS Model 3 : * Standard .MODEL N1 NMOS LEVEL=3 VTO=0.60 UO=600.000 TOX=10.0E-9 +LD =0.000U THETA=0.300 GAMMA=0.400 +PHI=0.300 KAPPA=0.010 VMAX=130.00K +CGSO=100.0p CGDO=100.0p +CGBO= 60.0p CJSW=240.0p * * p-MOS Model 3: * Standard .MODEL P1 PMOS LEVEL=3 VTO=-0.60 UO=200.000 TOX=10.0E-9 +LD =0.000U THETA=0.300 GAMMA=0.400 +PHI=0.300 KAPPA=0.010 VMAX=100.00K +CGSO=100.0p CGDO=100.0p +CGBO= 60.0p CJSW=240.0p * * Transient analysis * .TEMP 27.0 .TRAN 0.1N 20.00N * (Pspice) .PROBE .END 4. Dc analysis:
DISCUSSION:After doing this experiment we have gained the knowledge about the CMOS Inverter construction using the Microwind2 software. But we have faced few problems when the experiment was going on, due to the software’s incorrectness. . More 4 Lab reports on VLSI-1 Lab: |
| Last Updated on Wednesday, 02 September 2009 16:51 |

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